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NTQS6463 Power MOSFET
-20 V, -6.8 A, P-Channel TSSOP-8
Features
* * * * * * *
New Low Profile TSSOP-8 Package Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperatures Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones Lithium Ion Battery Applications Note Book PC
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VDSS -20 V RDS(on) TYP 20 mW @ -10 V ID MAX -6.8 A
Applications
* Power Management in Portable and Battery-Powered Products, i.e.: * *
P-Channel D
G
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Drain-to-Source Voltage Gate-to-Source Voltage Drain Current (Note 1) - Continuous @ TA = 25C - Continuous @ TA = 70C - Pulsed (Note 3) Total Power Dissipation (Note 1) @ TA = 25C Drain Current (Note 2) - Continuous @ TA = 25C - Continuous @ TA = 70C - Pulsed (Note 3) Total Power Dissipation (Note 2) @ TA = 25C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 40 V, IL = 18.4 A, L = 5.0 mH, RG = 25 W) Thermal Resistance - Junction-to-Ambient (Note 1) Junction-to-Ambient (Note 2) Symbol VDSS VGS ID ID IDM PD Value -20 "12 -5.5 -4.4 "30 0.93 W 1 A ID ID IDM PD TJ, Tstg EAS -6.8 -5.4 "30 1.39 -55 to +150 845 W C mJ D S S G 463 Y WW N = Device Code = Year = Work Week = MOSFET Unit V V A 8 TSSOP-8 CASE 948S PLASTIC S
MARKING DIAGRAM
463 YWW N
PIN ASSIGNMENT
1 2 3 4 Top View 8 7 6 5 D S S D
RqJA 134 90
C/W
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Minimum 3 X 3 FR-4 board, steady state. 2. Mounted on 1 square (1 oz.) board, steady state. 3. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
ORDERING INFORMATION
Device NTQS6463 NTQS6463R2 Package TSSOP-8 TSSOP-8 Shipping 100 Units/Rail 3000/Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2004
1
September, 2004 - Rev. 2
Publication Order Number: NTQS6463/D
NTQS6463
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic STATIC Gate Threshold Voltage (VDS = VGS, ID = -250 A) Gate-Body Leakage (VGS = 0 V, VGS = 8 V) Zero Gate Threshold Voltage Drain Current (VDS = -16 V, VGS = 0 V) (VDS = -16 V, VGS = 0 V, TJ = 70_C) Drain-Source On-State Resistance (Note 4) (VGS = -4.5 V, ID = -6.8 A) (VGS = -2.5 V, ID = -5.5 A) Forward Transconductance (VDS = -15 V, ID = -6.8 A) (Note 4) Diode Forward Voltage (IS = -1.3 A, VGS = 0 V) (Note 4) DYNAMIC Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time (VDD = -10 V, 10 V ID -1.0 A, 1.0 VGS = -4.5 V, RG = 6.0 ) 60 (IF = -1.3 A, di/dt = 100 A/s) (VDS = -10 V, VGS = -5.0 V, ID = -6.8 A) 68 Qg Qgs Qgd td(on) tr td(off) tf trr - - - - - - - - 28 5.5 9.0 15 22 90 53 45 50 - - 25 40 150 90 80 ns ns nC VGS(th) IGSS IDSS - - RDS(on) - - gFS VSD - - 0.016 0.022 21 -0.71 0.020 0.027 - -1.1 S V - - -1.0 -10 -0.45 - -0.9 - - 100 V nA Symbol Min Typ Max Unit
4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
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NTQS6463
10 -ID, DRAIN CURRENT (A) 16 -2.2 V -2.4 V -2.8 V -4 V -6 V -10 V -2 V -ID, DRAIN CURRENT (A) 12 VDS -10 V
8
TJ = 25C -1.8 V
6
8
TJ = 25C TJ = 100C
4
2 0 0 0.25 0.5 0.75 1 1.25 1.5
-1.6 V VGS = -1.4 V
4 TJ = -55C 0
1.75
2
0
0.5
1
1.5
2
2.5
-VDS, DRAIN-TO-SOURCE VOLTAGE (V)
-VGS, GATE-TO-SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0.05 RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0.03
Figure 2. Transfer Characteristics
TJ = 25C 0.025 VGS = -2.5 0.02 VGS = -4.5 0.015
0.04
ID = -7.4 A TJ = 25C
0.03
0.02
0.01 0 0 2 4 6 8 10 -VGS, GATE-TO-SOURCE VOLTAGE (V)
0.01 2 4 6 8 10 12 14 -ID, DRAIN CURRENT (A)
Figure 3. On-Resistance versus Gate-to-Source Voltage
1.6 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) ID = -7.4 A VGS = -4.5 V 1000
Figure 4. On-Resistance versus Drain Current and Gate Voltage
VGS = 0 V -IDSS, LEAKAGE (nA)
1.4
TJ = 125C
1.2
100 TJ = 100C
1
0.8 0.6 -50 10 -25 0 25 50 75 100 125 150 4 8 12 16 20 TJ, JUNCTION TEMPERATURE (C) -VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 5. On-Resistance Variation versus Temperature
Figure 6. Drain-to-Source Leakage Current versus Voltage
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NTQS6463
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP)
6000 Ciss 5000 C, CAPACITANCE (pF) 4000 Crss 3000 2000 1000 0 -10 Crss -5 VGS 0 VDS 5 10 15 20 Ciss VDS = 0 V VGS = 0 TJ = 25C
The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
Coss
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
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NTQS6463
-VDS, DRAIN-TO-SOURCE VOLTAGE (V) -VGS, GATE-TO-SOURCE VOLTAGE (V) 5 QT 4 VGS = -4.5 3 Q1 2 Q2 1000 VDD = -16 V ID = -6.8 A VGS = -4.5 V tf t, TIME (ns) td(off) 100 tr
1 0 0 4 8 12 16 20
TJ = 25C ID = -6.8 A 24 28
td(on)
10 1 10 RG, GATE RESISTANCE (W) 100
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate-to-Source and Drain-to-Source Voltage versus Total Charge
100 -IS, SOURCE CURRENT (A) 1.2 -ID, DRAIN CURRENT (A) VGS = 0 V TJ = 25C
Figure 9. Resistive Switching Time Variation versus Gate Resistance
Mounted on 2 sq. FR4 board (1 sq. 1 oz. Cu 0.06 thick single sided)
10
10 ms 100 ms 1 ms 10 ms
0.8
1 VGS = -4.5 V SINGLE PULSE TC = 25C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 dc
0.4
0.1
0 0.4 0.5 0.6 0.7 -VSD, SOURCE-TO-DRAIN VOLTAGE (V)
0.01 0.1
100
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
Figure 11. Maximum Rated Forward Biased Safe Operating Area
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr, tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature. Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
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NTQS6463
PACKAGE DIMENSIONS
TSSOP-8 CASE 948S-01 ISSUE O
K REF 0.10 (0.004) L/2
8 5 M
8x
0.20 (0.008) T U
S
TU
S
V
S
L
1 PIN 1 IDENT 4
B -U-
J J1
0.20 (0.008) T U
S
A -V- C
0.076 (0.003) D -T- SEATING
PLANE
G
DETAIL E
P N P1
N
DETAIL E
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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EEEE CCC EEEE CCC
K1 K SECTION N-N -W- 0.25 (0.010) M F
2X
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 2.90 3.10 4.30 4.50 --- 1.10 0.05 0.15 0.50 0.70 0.65 BSC 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ --- 2.20 --- 3.20 INCHES MIN MAX 0.114 0.122 0.169 0.177 --- 0.043 0.002 0.006 0.020 0.028 0.026 BSC 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ --- 0.087 --- 0.126
DIM A B C D F G J J1 K K1 L M P P1
NTQS6463/D

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